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HD404054 Series/HD404094 Series
Rev. 6.0 Sept. 1998 Description
The HD404054 Series and HD404094 Series are HMCS400-series microcomputers designed to increase program productivity with large-capacity memory. Each microcomputer has three timers, one serial interface, comparator, input capture circuit. The HD404054 Series includes three chips: the HD404052 with 2-kword ROM; the HD404054 with 4kword ROM; and the HD4074054 with 4-kword PROM (ZTATTM version). Also, the HD404094 Series includes three chips: the HD404092 with 2-kword ROM; the HD404094 with 4-kword ROM; and the HD4074094 with 4-kword PROM (ZTATTM version). The HD4074054 and HD4074094 are PROM version (ZTATTM microcomputers). Program can be written to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (The ZTATTMversion is 27256-compatible.)
Features
* The differences between HD404054 Series and HD404094 Series
HD404054 Series I/O pins 10 large-current output pins: Six 15-mA sinks and four 10-mA sources HD404094 Series * * 6 largecurrent output pins: Two 15-mA sinks and four 10-mA sources 4 intermediate voltage output pins
* * * * * * * *
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27 I/O pins and 8 dedicated input pins Three timer/counters Eight-bit input capture circuit Two timer outputs (including two PWM outputs) One event counter inputs (including one double-edge function) One clock-synchronous 8-bit serial interface Comparator (2 channels) Built-in oscillators Main clock: Ceramic or crystal oscillator (an external clock is also possible)
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HD404054 Series/HD404094 Series
* Six interrupt sources Two by external sources Four by internal sources * Subroutine stack up to 16 levels, including interrupts * Two low-power dissipation modes Standby mode Stop mode * One external input for transition from stop mode to active mode * Instruction cycle time: 1 s (fOSC = 4 MHz at 1/4 division ratio) 1/4, or 1/32 division ratio can be selected by hardware * Two operating modes MCU mode MCU/PROM mode (HD4074054, HD4074094)
Ordering Information
Product Name Type Mask ROM HD404054 Series HD404052H HD404052S HD40A4052H HD40A4052S HD404054H HD404054S HD40A4054H HD40A4054S ZTATTM HD4074054H HD4074054S ZTATTM: Zero Turn Around Time HD4074094H HD4074094S ZTAT is a trademark of Hitachi, Ltd. 4,096 HD404094H HD404094S 4,096 HD404094 Series HD404092H HD404092S ROM (words) 2,048 RAM (digit) 512 Package FP-44A DP-42S FP-44A DP-42S FP-44A DP-42S FP-44A DP-42S FP-44A DP-42S
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Pin Arrangement
RD 0 /COMP0 RD 1 /COMP1 RD2 RD3 RC0 RE 0 /VCref TEST OSC1 OSC2 RESET GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VCC SEL R43 /SO1 R42 /SI 1 R41 /SCK1 R40 /EVND R33 R32 /TOD R31 /TOC R30 R23 R22 R21 R20 R13 R12 R11 R10 R00 /INT1 D13 /INT0 D12 /STOPC
DP-42S
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D5 D6 D7 D8 D9 D12 /STOPC D 13 /INT0 R0 0 /INT1 R10 R11 NC
12 13 14 15 16 17 18 19 20 21 22
RE0/VCref TEST OSC1 OSC2 RESET GND D0 D1 D2 D3 D4
44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11
NC RC0 RD3 RD2 RD1 /COMP1 RD0 /COMP0 VCC SEL R4 3 /SO 1 R4 2 /SI1 R4 1 /SCK 1
FP-44A
33 32 31 30 29 28 27 26 25 24 23
R40 /EVND R33 R32 /TOD R31 /TOC R30 R23 R22 R21 R20 R13 R12
Top view
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Pin Description
Pin Number Item Symbol DP-42S 42 11 7 10 8 9 12-21 FP-44A 38 6 2 5 3 4 7-16 I I I O I/O* Input/output pins addressed by individual bits; pins D0-D 3 are high-current source pins that can each supply up to 10 mA. The HD404054 Series: pins D 4-D 9are high-current sink pins that can each supply up to 15mA. The HD404094 Series: D 4-D 7 are intermediate voltage (12 V) NMOS open-drain pins, and D8, D9 are high-current sink pins that can each supply up to 15 mA. D12,D13 R0 0-R4 3 RD0-RD3, RC0, RE 0 Interrupt Stop clear Serial INT0, INT1 STOPC SCK 1 SI 1 SO1 Timer 23, 24 22 38 39 40 18, 19 17 34 35 36 30, 31 33 39, 40 I I I/O I O O I I Input pins for external interrupts Input pin for transition from stop mode to active mode Serial clock input/output pin Serial receive data input pin Serial transmit data output pin Timer output pins Event count input pins Analog input pins for voltage comparator 22, 23 24-40 1-6 17, 18 19-36 I I/O Input pins addressable by individual bits Input/output pins addressable in 4-bit units Input pins addressable in 4-bit units I/O Function Applies power voltage Connected to ground Used for factory testing only: Connect this pin to VCC Resets the MCU
Power supply VCC GND Test Reset Oscillator TEST RESET OSC 1 OSC 2 Port D0-D 9
39-43,1 I
TOC, TOD 34, 35 EVND 37 1, 2
Comparator
COMP0, COMP1 VC ref
6 41
1 37 I
Reference voltage pin for inputting the threshold voltage of the analog input pin. Input pin for selecting system clock division rate after RESET input or after stop mode cancellation. 1/4 division rate: Connect it to V CC 1/32 division rate: Connect it to GND
Division rate SEL
Note: * D4-D 7 of the HD404094 Series are output pins.
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Block Diagram
STOPC RESET OSC 1 OSC 2 TEST
System control D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 High current source pins High current sink pins Intermediate voltage NMOS open-drain output pins*
INT0 INT1
External interrupt
Timer A
W (2bit)
X (4bit) D 12 D 13 TOC Timer C
RE port RC port RD port R4 port R3 port R2 port R1 port R0 port
D port
RAM (512 x 4bit)
GND
SEL
V CC
SPX (4bit)
R0 0 R10 R11 R12 R13 R2 0 R2 1 R2 2 R2 3 R3 0 R3 1 R3 2 R3 3 R4 0 R4 1 R4 2 R4 3 RD0 RD1 RD2 RD3 RC0
EVND TOD SI1 SO1 SCK1 VCref COMP0 COMP1
Timer D
Y (4bit)
Internal address bus
Serial 1
SPY (4bit)
Comparator
Internal data bus
ALU CPU ST CA (1bit) (1bit)
Internal data bus
A (4bit)
RE 0
B (4bit)
SP (10bit) Instruction decoder
PC (14bit)
ROM (4,096 x 10bit) (2,048 x 10bit)
Note: * Only HD404094 Series
: Data bus : Signal line
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Memory Map
ROM Memory Map The ROM memory map is shown in figure 1 and described below. Vector Address Area ($0000-$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the vector address. Zero-Page Subroutine Area ($0000-$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000-$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000-$07FF (HD404052, HD40A4052, HD404092), $0000-$0FFF (HD404054, HD40A4054, HD4074054, HD404094, HD4074094)): Used for program coding.
0
Vector address 15 16 Zero-page subroutine (64 words) 63 64 Program & Pattern 2048 words (HD404052, HD40A4052, HD404092) 4096 words (HD404054, HD40A4054, HD4074054,HD404094, HD4074094) 4095 $0FFF $003F $0040 $000F $0010
$0000
0 JMPL instruction 1 (Jump to RESET, STOPC routine) JMPL instruction 2 (Jump to INT0 routine) 3 JMPL instruction 4 (Jump to INT1 routine) 5 6 7 8 9 10 11 12 13 14 15 JMPL instruction (Jump to timer A routine) Not used JMPL instruction (Jump to timer C, routine) JMPL instruction (Jump to timer D, routine) JMPL instruction (Jump to serial 1 routine)
2047
$07FF
$0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F
Figure 1 ROM Memory Map RAM Memory Map The MCU contains a 512-digit x 4-bit RAM area consisting of a memory register area, a data area, and a stack area. In addition, an interrupt control bits area, special register area, and register flag area are mapped onto the same RAM memory space as a RAM-mapped register area outside the above areas. The RAM memory map is shown in figure 2 and described as follows.
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0 RAM-mapped registers 64 80 Not used 144 $090 Memory registers (MR) $040 $050 $000 0 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Interrupt control bits area
(PMRA) W Port mode register A Serial mode register 1A (SM1A) W Serial data register 1 lower (SR1L) R/W Serial data register 1 upper (SR1U) R/W Timer mode register A (TMA) W
$000 $003 $004 $005 $006 $007 $008 $009 $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019
Not used
(MIS) Miscellaneous register Timer mode register C1 (TMC1) (TRCL/TWCL) Timer C (TRCU/TWCU) Timer mode register D1 (TMD1) (TRDL/TWDL) Timer D (TRDU/TWDU) Not used Timer mode register C2 (TMC2) Timer mode register D2 (TMD2) Not used Compare data register (CDR) (CER) Compare enable register
Data (432 digits)
576 Not used 960 Stack (64 digits) 1023
$240
W W R/W R/W W R/W R/W R/W R/W R W
$3C0 $3FF
Not used R: Read only W: Write only R/W: Read/Write
31 32 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
Register flag area Port mode register B (PMRB) (PMRC) Port mode register C Not used
Detection edge select register 2 (ESR2)
W W W W
Serial mode register 1B Not used Port D0 to D3 DCR Port D4 to D 7 DCR Port D8 and D9 DCR Not used Port R0 DCR Port R1 DCR Port R2 DCR Port R3 DCR Port R4 DCR
(SM1B)
$01F $020 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035
(DCD0) (DCD1) (DCD2) (DCR0) (DCR1) (DCR2) (DCR3) (DCR4)
W W W W W W W W
Not used
Two registers are mapped on the same area.
63
$03F
14 Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W $00E 15 Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W $00F 17 Timer read register D lower (TRDL) R Timer write register D lower (TWDL) W $011 18 Timer read register D upper (TRDU) R Timer write register D upper (TWDU) W $012
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Figure 2 RAM Memory Map
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RAM-Mapped Register Area ($000-$03F): * Interrupt Control Bits Area ($000-$003) This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. * Special Function Register Area ($004-$018, $024-$034) This area is used as mode registers and data registers for external interrupts, serial interface 1, timer/counters, voltage comparator, and as data control registers for I/O ports. The structure is shown in figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and read/write (R/W). RAM bit manipulation instructions cannot be used for these registers. * Register Flag Area ($020-$023) This area is used for the WDON, and other register flags and interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. Memory Register (MR) Area ($040-$04F): Consisting of 16 addresses, this area (MR0-MR15) can be accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6. Data Area ($090-$23F): 432 digits from $090 to $23F. Stack Area ($3C0-$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save conditions are shown in figure 6. The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any unused space in this area is used for data storage.
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Bit 3
0
Bit 2
Bit 1
Bit 0
IE (Interrupt enable flag)
$000
IM0 (IM of INT0)
IF0 (IF of INT0)
RSP (Reset SP bit)
1
IMTA (IM of timer A)
IMTC (IM of timer C)
IMS1 (IM of serial interface 1)
IFTA (IF of timer A) IFTC (IF of timer C)
IFS1 (IF of serial interface 1)
IM1 (IM of INT1)
Not used
IF1 (IF of INT1)
Not used IFTD (IF of timer D)
$001
2
$002
3
IMTD (IM of timer D)
$003
Interrupt control bits area
Bit 3
32
Bit 2
Bit 1
WDON (Watchdog on flag)
Bit 0
Not used
ICSF (Input capture status flag)
$020
Not used
RAME (RAM enable flag)
Not used
33
Not used
ICEF (Input capture error flag)
IF: IM: IE: SP:
Interrupt request flag Interrupt mask Interrupt enable flag Stack pointer
$021
Register flag area
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
SEM/SEMD IE IM IF ICSF ICEF RAME RSP WDON Not used Allowed REM/REMD Allowed TM/TMD Allowed
Not executed Not executed Allowed Not executed
Allowed Allowed Not executed Not executed
Allowed Inhibited Inhibited Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. If the TM or TDM instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
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Bit 3 $000 $003 PMRA $004 SM1A $005 SR1L $006 SR1U $007 TMA $008 R41/SCK1 Bit 2 Bit 1 Bit 0 : Not used R43/SO1 Interrupt control bits area R42/SI1 Serial data register 1 (lower digit) Serial data register 1 (upper digit) Clock source selection (timer A)
Serial transmit clock speed selection 1
MIS $00C TMC1 $00D TRCL/TWCL $00E TRCU/TWCU $00F TMD1 $010 TRDL/TWDL $011 TRDU/TWDU $012 $013 TMC2 $014 TMD2 $015 $016 CDR $017 CER $018
*2 *1
SO 1 PMOS control Clock source selection (timer C) Timer C register (lower digit) Timer C register (upper digit)
*1
Clock source selection (timer D) Timer D register (lower digit) Timer D register (upper digit) Timer-C output mode selection
*3
Timer-D output mode selection Result of each analog input comparison *5
*4
$020 $023 PMRB $024 PMRC $025 D13/INT0
Register flag area R00/INT1 D12/STOPC R40/EVND
$026 ESR2 $027 EVND detection edge selection SM1B $028 *6 *7
DCD0 $02C DCD1 $02D DCD2 $02E DCR0 $030 DCR1 $031 DCR2 $032 DCR3 $033 DCR4 $034
Port D3 DCR Port D2 DCR Port D7 DCR Port D6 DCR
Port D1 DCR Port D0 DCR Port D5 DCR Port D4 DCR Port D9 DCR Port D8 DCR Port R0 0 DCR
Port R13 DCR Port R1 2 DCR Port R1 1 DCR Port R1 0 DCR Port R2 3 DCR Port R2 2 DCR Port R2 1 DCR Port R2 0 DCR Port R3 3 DCR Port R3 2 DCR Port R3 1 DCR Port R3 0 DCR Port R4 3 DCR Port R4 2 DCR Port R4 1 DCR Port R4 0 DCR Notes: 1. Auto-reload on/off 2. Pull-up MOS control 3. Input capture selection 4. Comparator switch 5. Port/comparator selection 6. SO1 output level control in idle states 7. Serial clock source selection 1
$03F
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Figure 5 Special Function Register Area
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Memory registers MR(0) $040 64 MR(1) $041 65 MR(2) $042 66 MR(3) $043 67 MR(4) $044 68 MR(5) $045 69 MR(6) $046 70 MR(7) $047 71 MR(8) $048 72 MR(9) $049 73 MR(10) $04A 74 MR(11) $04B 75 MR(12) $04C 76 MR(13) $04D 77 MR(14) $04E 78 MR(15) $04F 79 Stack area Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 1023 Level 1 960 $3C0
Bit 3 1020 1021 1022 $3FF 1023 ST PC 10 CA PC 3
Bit 2 PC13 PC9 PC6 PC2
Bit 1 PC 12 PC 8 PC 5 PC 1
Bit 0 PC11 PC7 PC4 PC0 $3FC $3FD $3FE $3FF
PC13 -PC0 : Program counter ST: Status flag CA: Carry flag
Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position
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Functional Description
Registers and Flags The MCU has nine registers and two flags for CPU operations. They are shown in figure 7 and described below.
3 Accumulator Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W (B) 1 W register Initial value: Undefined, R/W 3 X register Initial value: Undefined, R/W 3 Y register Initial value: Undefined, R/W 3 SPX register Initial value: Undefined, R/W 3 SPY register Initial value: Undefined, R/W (SPY) 0 Carry Initial value: Undefined, R/W (CA) 0 Status Program counter Initial value: 0, no R/W Stack pointer Initial value: $3FF, no R/W Initial value: 1, no R/W 13 (PC) 9 1 1 1 1 5 (SP) 0 (ST) 0 (SPX) 0 (Y) 0 (X) 0 0 (W) 0 (A) 0 0
Figure 7 Registers and Flags Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit (ALU) and transfer data between memory, I/O, and other registers. W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for indirect RAM addressing. www..com The Y register is also used for D-port addressing.
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SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers. Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction-but not by the RTN instruction. Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction. Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being executed. Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a stack can be used up to 16 levels. The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD instruction. Reset The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is cancelled, RESET must be high for at least one tRC to enable the oscillator to stabilize. During operation, RESET must be high for at least two instruction cycles. Initial values after MCU reset are listed in table 1.
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Table 1
Item Program counter Status flag Stack pointer Interrupt flags/mask Interrupt enable flag Interrupt request flag Interrupt mask I/O Port data register Data control register
Initial Values After MCU Reset
Abbr. (PC) (ST) (SP) (IE) (IF) (IM) (PDR) Initial Value $0000 1 $3FF 0 0 1 Contents Indicates program execution point from start address of ROM area Enables conditional branching Stack level 0 Inhibits all interrupts Indicates there is no interrupt request Prevents (masks) interrupt requests
All bits 1 Enables output at level 1
(DCD0 - All bits 0 Turns output buffer off (to high impedance) DCD2) (DCR0- DCR4) All bits 0 - - 00 ---0 Refer to description of port mode register A Refer to description of port mode register B Refer to description of port mode register C
Port mode register A Port mode register B Port mode register C bits 3, 2, 1 Detection edge select register 2 Timer/ counters, serial interface Timer mode register A
(PMRA) (PMRB)
(PMRC3, 000 PMRC2, PMRC1) (ESR2) (TMA) 00 - - 000 0000 - 000 0000 0000 0000 - - X0 $000 $00 $00 $00 $X0 $X0 000 0 - 00
Disables edge detection Refer to description of timer mode register A Refer to description of timer mode register C1 Refer to description of timer mode register C2 Refer to description of timer mode register D1 Refer to description of timer mode register D2 Refer to description of serial mode register 1A Refer to description of serial mode register 1B -- -- -- -- -- -- -- Refer to description of voltage comparator
Timer mode register C1 (TMC1) Timer mode register C2 (TMC2) Timer mode register D1 (TMD1) Timer mode register D2 (TMD2) Serial mode register 1A (SM1A) Serial mode register 1B (SM1B) Prescaler S Timer counter A Timer counter C Timer counter D Timer write register C Timer write register D Octal counter (PSS) (TCA) (TCC) (TCD) (TWCU, TWCL) (TWDU, TWDL) (CER)
Comparator Compare enable register
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Item Bit register Watchdog timer on flag Abbr. Initial Value Contents Refer to description of timer C Refer to description of timer D Refer to description of timer D Refer to description of operating modes, and oscillator circuit
(WDON) 0 0 0 00 - -
Input capture status flag (ICSF) Input capture error flag Others Miscellaneous register (ICEF) (MIS)
Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. - indicates that the bit does not exist
Item Carry flag
Abbr. (CA)
Status After Status After Cancellation of Stop Cancellation of Stop Mode by STOPC Input Mode by MCU Reset Pre-stop-mode values are not guaranteed; values must be initialized by program
Status After all Other Types of Reset Pre-MCU-reset values are not guaranteed; values must be initialized by program
Accumulator B register W register X/SPX register Y/SPY register Serial data register RAM RAM enable flag
(A) (B) (W) (X/SPX) (Y/SPY) (SRL, SRU) Pre-stop-mode values are retained (RAME) 1 Pre-stop-mode values are retained 0 0 0 0
Port mode register 1 (PMRC12) bit 2
Interrupts The MCU has 6 interrupt sources: Two external signals (INT0, INT1), Three timer/counters (timers A, C, and D), and one serial interface (serial 1). An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt source, and an interrupt enable flag (IE) controls the entire interrupt process. Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $020 to $021 in RAM are reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions. The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE) and the IF to 0 and the interrupt mask (IM) to 1.
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A block diagram of the interrupt control circuit is shown in figure 8, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the 6 interrupt sources are listed in table 3. An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to that interrupt source. The interrupt processing sequence is shown in figure 9 and an interrupt processing flowchart is shown in figure 10. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. Program the JMPL instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the IF by a software instruction within the interrupt program. Table 2 Vector Addresses and Interrupt Priorities
Priority -- 1 2 3 4 5 6 7 Vector Address $0000 $0002 $0004 $0006 $0008 $000A $000C $000E
Reset/Interrupt RESET, STOPC* INT0 INT1 Timer A Not used Timer C Timer D Serial 1
Note: * The STOPC interrupt request is valid only in stop mode.
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$ 000,0 IE $ 000,2 IFO $ 000,3 IMO Priority control logic INT1 interrupt $ 001,0 IF1 $ 001,1 IM1 $ 001,2 IFTA $ 001,3 IMTA Sequence control * Push PC/CA/ST * Reset IE * Jump to vector address
INT0 interrupt
Vector address
Timer A interrupt
Not used
Timer C interrupt
$ 002,2 IFTC $ 002,3 IMTC
Timer D interrupt
$ 003,0 IFTD $ 003,1 IMTD $ 003,2
Serial 1 interrupt
IFS1 $ 003,3 IMS1
Note: $m,n is RAM address $m, bit number n.
Figure 8 Interrupt Control Circuit
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Table 3 Interrupt Processing and Activation Conditions
Interrupt Source Interrupt Control Bit IE IF0 * IM0 IF1 * IM1 IFTA * IMTA IFTC * IMTC IFTD * IMTD IFS1 * IMS1 INT0 1 1 * * * * * INT1 1 0 1 * * * * Timer A 1 0 0 1 * * * Timer C 1 0 0 0 1 * * Timer D 1 0 0 0 0 1 * Serial 1 1 0 0 0 0 0 1
Note: * Can be either 0 or 1. Their values have no effect on operation.
Instruction cycles 1 2 3 4 5 6
Instruction execution *
Interrupt acceptance
Stacking IE reset Vector address generation
Execution of JMPL instruction at vector address
Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction.
Execution of instruction at start address of interrupt routine
Figure 9 Interrupt Processing Sequence
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Power on
RESET = 0? Yes
No
Interrupt request? No
Yes
No
IE = 1? Yes
Reset MCU
Execute instruction
Accept interrupt
PC (PC) + 1
IE 0 Stack (PC) Stack (CA) Stack (ST)
PC $0002
Yes
INT0 interrupt? No
PC $0004
Yes
INT1 interrupt? No
PC $0006
Yes
Timer-A interrupt? No
PC $000A
Yes
Timer-C interrupt? No
PC $000C
Yes
Timer-D interrupt? No
PC $000E
(serial 1 interrupt)
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Figure 10 Interrupt Processing Flowchart
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Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction, as listed in table 4. Table 4
IE 0 1
Interrupt Enable Flag (IE: $000, Bit 0)
Interrupt Enabled/Disabled Disabled Enabled
External Interrupts (INT0, INT1): Two external interrupt signals. External Interrupt Request Flags (IF0, IF1: $000, $001): IF0 and IF1 are set the falling of signals input to INT0 and INT1 as listed in table 5. Table 5
IF0, IF1 0 1
External Interrupt Request Flags (IF0, IF1: $000, $001)
Interrupt Request No Yes
External Interrupt Masks (IM0, IM1: $000, $001): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. Table 6
IM0, IM1 0 1
ExternalInterrupt Masks (IM0, 1M1: $000, $001)
Interrupt Request Enabled Disabled (masked)
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in table 7. Table 7
IFTA 0 1
Timer A Interrupt Request Flag (IFTA: $001, Bit 2)
Interrupt Request No Yes
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Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer A interrupt request flag, as listed in table 8. Table 8
IMTA 0 1
Timer A Interrupt Mask (IMTA: $001, Bit 3)
Interrupt Request Enabled Disabled (masked)
Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in table 9. Table 9
IFTC 0 1
Timer C Interrupt Request Flag (IFTC: $002, Bit 2)
Interrupt Request No Yes
Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer C interrupt request flag, as listed in table 10. Table 10
IMTC 0 1
Timer C Interrupt Mask (IMTC: $002, Bit 3)
Interrupt Request Enabled Disabled (masked)
Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the rising or falling edge of signals input to EVND when the input capture function is used, as listed in table 11. Table 11
IFTD 0 1
Timer D Interrupt Request Flag (IFTD: $003, Bit 0)
Interrupt Request No Yes
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Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the timer D interrupt request flag, as listed in table 12. Table 12
IMTD 0 1
Timer D Interrupt Mask (IMTD: $003, Bit 1)
Interrupt Request Enabled Disabled (masked)
Serial Interrupt Request Flags (IFS1: $003, Bit 2): Set when data transfer is completed or when data transfer is suspended, as listed in table 13. Table 13
IFS1 0 1
Serial Interrupt Request Flag (IFS1: $003, Bit 2)
Interrupt Request No Yes
Serial Interrupt Masks (IMS1: $003, Bit 3): Prevents (masks) an interrupt request caused by the serial interrupt request flag, as listed in table 14. Table 14
IMS1 0 1
Serial Interrupt Mask (IMS1: $003, Bit 3)
Interrupt Request Enabled Disabled (masked)
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Operating Modes
The MCU has Three operating modes as shown in table 15. The operations in each mode are listed in tables 16 and 17. Transitions between operating modes are shown in figure 11. Table 15 Operating Modes and Clock Status
Mode Name Active Activation method Standby Stop STOP instruction
SBY instruction RESET cancellation, interrupt request, STOPC cancellation in stop mode OP OP
Status
System oscillator
Stopped
Cancellation method Note: OP implies in operation
RESET input, RESET input, interrupt RESET input, STOPC STOP/SBY instruction request input in stop mode
Table 16
Function CPU RAM Timer A Timer C Timer D
Operations in Low-Power Dissipation Modes
Stop Mode Reset Retained Reset Reset Reset Reset Reset Reset* Standby Mode Retained Retained OP OP OP OP Stopped Retained
Serial interface 1 Comparator I/O
Note: OP implies in operation * Output pins are at high impedance.
Table 17
I/O Status in Low-Power Dissipation Modes
Output Standby Mode Stop Mode High impedance -- Input Active Mode Input enabled Input enabled
D0-D 9 D12, D13, RC0, RD0-RD3, RE 0 R0-R4
Retained --
Retained or output of peripheral functions
High impedance
Input enabled
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Reset by RESET input or by watchdog timer fOSC: Main oscillation frequency fcyc: f OSC/4 or or fOSC /32 (hardware selectable) o CPU: System clock o PER: Clock for other peripheral functions
RAME = 0 RESET1
RAME = 1 RESET2
STOPC
Active mode
Standby mode SBY Interrupt
Stop mode
(TMA3 = 0)
fOSC: Oscillate o CPU: Stop o PER: fcyc
fOSC: Oscillate o CPU: fcyc o PER: fcyc
STOP
fOSC: o CPU: o PER:
Stop Stop Stop
Figure 11 MCU Status Transitions Active Mode: All MCU functions operate according to the clock generated by the system oscillators OSC1 and OSC2. Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and serial interface continue to operate. The power dissipation in this mode is lower than in active mode because the CPU stops. The MCU enters standby mode when the SBY instruction is executed in active mode. Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input, the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation in standby mode is shown in figure 12.
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Stop Standby
Oscillator: Stop Peripheral clocks: Stop All other clocks: Stop
Oscillator: Active Peripheral clocks: Active All other clocks: Stop
No
RESET = 0?
RESET = 0?
No
Yes No
STOPC = 0?
Yes
IF0 * IM0 = 1?
No
Yes Yes
IF1 * IM1 = 1?
No
Yes
IFTA * IMTA = 1?
No
Yes
RAME = 1
RAME = 0
IFTC * IMTC = 1?
No
Yes
IFTD * IMTD = 1?
No
Yes
IFS1 * IMS1 = 1?
No
Yes
Restart processor clocks
Restart processor clocks Execute next instruction
No
IF = 1, IM = 0, and IE = 1?
Yes
Reset MCU
Execute next instruction
Accept interrupt
Figure 12 MCU Operation Flowchart Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power dissipation in this mode is the least of all modes. The OSC 1 and OSC2 oscillator stops. The MCU enters stop mode if the STOP instruction is executed in active mode. Stop mode is terminated by a RESET input or a STOPC input as shown in figure 13. RESET or STOPC must be applied for at least one tRC to stabilize oscillation (refer to the AC Characteristics section). When the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained, but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and serial data register cannot be guaranteed.
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Stop mode Oscillator Internal clock STOP or RESET tres STOP instruction execution tres tRC (stabilization period)
Figure 13 Timing of Stop Mode Cancellation
Stop Mode Cancellation by STOPC: The MCU enters active mode from stop mode by inputting STOPC as well as by RESET. In either case, the MCU starts instruction execution from the starting address (address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs between cancellation by STOPC and by RESET. When stop mode is cancelled by RESET, RAME = 0; when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop mode; STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop mode has been cancelled by STOPC (for example, when the RAM contents before entering stop mode is used after transition to active mode), execute the TEST instruction to the RAM enable flag (RAME) at the beginning of the program. MCU Operation Sequence: The MCU operates in the sequences shown in figures 14 to 16. It is reset by an asynchronous RESET input, regardless of its status.
The low-power mode operation sequence is shown in figure 16. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked.
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Power on
RESET = 0? Yes RAME = 0
No
MCU operation cycle
Reset MCU
Figure 14 MCU Operating Sequence (Power On)
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MCU operation cycle
IF = 1?
Yes
No
No
IM = 0 and IE = 1?
Instruction execution
Yes
Yes
SBY/STOP instruction?
IE 0 Stack (PC), (CA), (ST)
No
Low-power mode operation cycle
PC Next location
PC Vector address
IF: IM: IE: PC: CA: ST:
Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag
Figure 15 MCU Operating Sequence (MCU Operation Cycle)
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Low-power mode operation cycle
IF = 1 and IM = 0?
No
Yes
Standby mode Stop mode
No
IF = 1 and IM = 0?
No
STOPC = 0?
Yes Hardware NOP execution Hardware NOP execution
Yes
RAME = 1
PC Next Iocation
PC Next Iocation
Reset MCU
Instruction execution
MCU operation cycle For IF and IM operation, refer to figure 12.
Figure 16 MCU Operating Sequence (Low-Power Mode Operation)
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Internal Oscillator Circuit
A block diagram of the clock generation circuit is shown in figure 17. As shown in table 18, a ceramic oscillator can be connected to OSC 1 and OSC2. The system oscillator can also be operated by an external clock. After RESET input or after stop mode has been cancelled, the division ratio of the system clock can be selected as 1/4 or 1/32 by setting the SEL pin level. * 1/4 division ratio: Connect SEL to VCC. * 1/32 division ratio: Connect SEL to GND.
OSC2 OSC1
System fOSC oscillator
1/4 or 1/32 division circuit*
fcyc tcyc
Timing generator circuit
CPU
CPU with ROM, RAM, registers, flags, and I/O
PER
Peripheral function interrupt
Note: * 1/4 or 1/32 division ratio can be selected by SEL pin.
Figure 17 Clock Generation Circuit
RE 0 TEST OSC 1 OSC 2 RESET GND GND
Figure 18 Typical Layout of Ceramic Oscillator
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Table 18 Oscillator Circuit Examples
Circuit Configuration External clock operation
External oscillator OSC 1
Circuit Constants
Open
OSC 2
Ceramic oscillator (OSC1, OSC 2)
C1 OSC1 Ceramic oscillator Rf OSC2 C2 GND
Ceramic oscillator: CSB400P22 (Murata), CSB400P (Murata) Rf = 1 M 20% C1 = C2 = 220 pF 5%
Ceramic oscillator: CSB800J122 (Murata), CSB800J (Murata) Rf = 1 M 20% C1 = C2 = 220 pF 5% Ceramic oscillator: CSA2.00MG (Murata) Rf = 1 M 20% C1 = C2 = 30 pF 20% Ceramic oscillator: CSA4.00MG (Murata) Rf = 1 M 20% C1 = C2 = 30 pF 20% Ceramic oscillator: CSA3.58MG (Murata) Rf = 1 M 20% C1 = C2 = 30 pF 20% Notes: 1. Since the circuit constants change depending on the ceramic oscillator and stray capacitance of the board, the user should consult with the ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC 2, and elements should be as short as possible, and must not cross other wiring (see figure 18).
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Input/Output
The MCU has 27 input/output pins (D0-D9, R0 0-R4 3) and 8 input pins (D12, D13, RC0, RD0- RD3, RE 0). The features are described below. Some input/output pins have different features between the HD404054 Series and HD404094 Series. The differences between the HD404054 Series and HD404094 Series are listed in table 19. * A maximum current of 15 mA is allowed for each of the pins D 4 to D9 with a total maximum current of less than 105 mA. In addition, D0-D3 can each act as a 10-mA maximum current source. * Some input/output pins are multiplexed with peripheral function pins such as for the timers or serial interface. For these pins, the peripheral function setting is done prior to the D or R port setting. Therefore, when a peripheral function is selected for a pin, the pin function and input/output selection are automatically switched according to the setting. * Input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software. * Peripheral function output pins are CMOS output pins. Only the R43/SO1 pin can be set to NMOS opendrain output by software. * In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output pins are in high-impedance state. * Pins D0-D3 have built-in pull-down MOSs, and other input/output pins have built-in pull-up MOSs, which can be individually turned on or off by software. I/O buffer configuration is shown in figure 19 programmable I/O circuits are listed in table 20, and I/O pin circuit types are shown in table 21. Table 19 The differences between HD404054 Series and HD404094 Series
HD404054 Series Large-current source pins (15 mA) Large-current sink pins (10 mA) Intermediate voltage NMOS open-drain pins (12 V) Pull-down MOS current pins Pull-up MOS current pins D0-D 3 D4-D 9 D0-D 3 D4-D 9, R0-R4 HD404094 Series D0-D 3 D8, D9 D4-D 7 (output only) D0-D 3 D8, D9, R0-R4
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Table 20-1 Programmable I/O Circuits (with pull-up MOS)
MIS3 (Bit 3 of MIS) DCD, DCR PDR CMOS buffer PMOS NMOS Pull-up MOS Note: -- indicates off status. 0 0 0 -- -- -- 1 -- -- -- 1 0 -- On -- 1 On -- -- 1 0 0 -- -- -- 1 -- -- On 1 0 -- On -- 1 On -- On
Table 20-2 Programmable I/O Circuits (with pull-down MOS)
MIS3 (Bit 3 of MIS) DCD, DCR PDR CMOS buffer PMOS NMOS Pull-down MOS Note: -- indicates off status. 0 0 0 -- -- -- 1 -- -- -- 1 0 -- On -- 1 On -- -- 1 0 0 -- -- On 1 -- -- -- 1 0 -- On On 1 On -- --
D4-D 9, R port (HD404054 Series) D8, D9, R port (HD404094 Series)
HLT VCC Pull-up MOS VCC Pull-up control signal MIS3
Buffer control signal DCD, DCR
Output data
PDR
Input data Input control signal
Figure 19-1 I/O Buffer Configuration (with pull-up MOS)
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D0-D 3 port
Input control signal VCC Input data
Buffer control signal DCD, DCR
Output data
PDR
MIS3 Pull-down control signal
HLT
Figure 19-2 I/O Buffer Configuration (with pull-down MOS)
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Table 21 Circuit Configurations of I/O Pins
Pins I/O Pin Type Circuit Input/output pins
VCC HLT VCC Pull-up control signal Buffer control signal Output data Input data Input control signal Input control signal MIS3 DCD, DCR PDR
HD404054 Series D4-D 9, R0-R4
HD404094 Series D8, D9, R0-R4
D0-D 3
Input data
D0-D 3
VCC
Buffer control signal
DCD, DCR
Output data
PDR MIS3
Pull-down control signal HLT
VCC HLT VCC Pull-up control signal Buffer control signal MIS3 DCR MIS2 PDR
R4 3
R4 3
Output data Input data Input control signal
Output pins
HLT
--
D4-D 7
DCD Output data PDR
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Pins I/O Pin Type Input pins Circuit
Input data Input control signal
HD404054 Series D12, D13, RC0
HD404094 Series D12, D13, RC0
RD0-RD3, RE 0 RD0-RD3, RE 0
HLT
Periphera Input/ l function output pins pins
VCC
VCC
Pull-up control signal
SCK 1
SCK 1
MIS3
Output data Input data SCK1
SCK1
Output pins
VCC
HLT VCC Pull-up control signal MIS3
SO1
SO1
PMOS control signal Output data
VCC
MIS2 SO1
HLT VCC Pull-up control signal MIS3
TOC, TOD
TOC, TOD
Output data
TOC, TOD
Input pins
VCC
HLT MIS3 PDR Input data SI1, INT1, EVND
SI 1, INT1, EVND
SI 1, INT1, EVND
Input data
INT0, INT0, STOPC STOPC
INT0, STOPC
Note: The MCU is reset in stop mode, and peripheral function selection is cancelled. The HLT signal becomes low, and input/output pins enter high-impedance state.
D Port (D0-D13): Consist of 10 input/output pins and 2 input pins addressed by one bit. D0-D3 are highcurrent sources, and D12 and D 13 are input-only pins. D4-D9 of the HD404054 Series are high-current sinks. D4-D7 of the HD404094 Series are middle voltage output-only pins, and D8 and D9 are high-current sink pins. Pins D 0-D 9 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions. Output data is stored in the port data register (PDR) for each pin. All pins D0-D13 are tested by the TD and TDD instructions.
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The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0-DCD2: $02C-$02E) that are mapped to memory addresses (figure 20). Pins D12 and D 13 are multiplexed with peripheral function pins S TOP C and INT0, respectively. The peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode register C (PMRC: $025) (figure 22). R Ports (R0 0-RE0): 17 input/output pins and 6 input pins addressed in 4-bit units. Data is input to these ports by the LAR and LBR instructions, and output from them by the LRA and LRB instructions. *Output data is stored in the port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled by R-port data control registers (DCR0-DCR4: $030-$034) that are mapped to memory addresses (figure 20). Pin R0 0 is are multiplexed with peripheral pin INT1 respectively. The peripheral function modes of these pins are selected by bit 0 (PMRB0) of port mode register B (PMRB: $024) (figure 21). Pins R31-R32 are multiplexed with peripheral pins TOC and TOD respectively. The peripheral function modes of these pins are selected by bits 0-2 (TMC20-TMC22) of timer mode register C2 (TMC2: $014), and bits 0-3 (TMD20-TMD23) of timer mode register D2 (TMD2: $015) (figures 23, and 24). Pin R40 is multiplexed with peripheral pin EVND respectively. The peripheral function modes of these pins are selected by bit 1 (PMRC1) of port mode register C (PMRC: $025) (figure 22). Pins R41-R43 are multiplexed with peripheral pins SCK 1, SI1, and SO1, respectively. The peripheral function modes of these pins are selected by bit 3 (SM1A3) of serial mode register 1A (SM1A: $005), and bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004), as shown in figures 25 and 26. Ports RD0 and RD1 are multiplexed with peripheral function pins COMP0 and COMP1, respectively. The function modes of these pins are selected by bit 3 (CER3) of the compare enable register (CER: $018) (figure 27). Port RE 0 is multiplexed with peripheral function pin VCref. While functioning as VC ref , do not use this pin as an R port at the same time, otherwise, the MCU may malfunction. Pull-Up or Pull-Down MOS Transistor Control: A program-controlled pull-up or pull-down MOS transistor is provided for each input/output pin other than input-only pins D 12 and D 13. The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding pin--enabling on/off control of that pin alone (table 20 and figure 28). The on/off status of each transistor and the peripheral function mode of each pin can be set independently. How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be connected to V CC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by their pull-up MOS transistors or by resistors of about 100 k or pulled down to GND by their pull-down MOS transistors. Note: *If nonexisted bits of R ports is read, undifined data will be latched to accumulator (A) or the B register.
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Data control register DCD0, DCD1 Bit Initial value Read/Write Bit name DCD2 Bit Initial value Read/Write Bit name DCR0 Bit Initial value Read/Write Bit name (DCD0 to 2: $02C to $02E) (DCR0 to 4: $030 to $034) 2 0 W 1 0 W 0 0 W
3 0 W
DCD03- DCD02- DCD01- DCD00- DCD13 DCD12 DCD11 DCD10 3 -- -- 2 -- -- 1 0 W 0 0 W DCD20
Not used Not used DCD21
3 -- --
2 -- --
1 -- --
0 0 W
Not used Not used Not used DCR00
DCR1 to DCR4 Bit Initial value Read/Write Bit name
3 0 W
2 0 W
1 0 W
0 0 W
DCR13- DCR12- DCR11- DCR10- DCR43 DCR42 DCR41 DCR40 CMOS Buffer On/Off Selection Off (high-impedance) On
All Bits 0 1
Correspondence between ports and DCD/DCR bits Register Name DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 Bit 3 D3 D7 -- -- R13 R23 R33 R43 Bit 2 D2 D6 -- -- R12 R22 R32 R42 Bit 1 D1 D5 D9 -- R11 R21 R31 R41 Bit 0 D0 D4 D8 R00 R10 R20 R30 R40
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Figure 20 Data Control Registers (DCD, DCR)
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Port mode register B (PMRB: $024) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 -- -- 0 0 W
Not used Not used Not used PMRB0
PMRB0 0 1
R00/INT1 mode selection R00 INT1
Figure 21 Port Mode Register B (PMRB)
Port mode register C (PMRC: $025) Bit Initial value Read/Write Bit name 3 0 W 2 0 W 1 0 W 0 -- --
PMRC3 PMRC2*
PMRC1 Not used
PMRC1 0 1 PMRC2 0 1 PMRC3 0 1
R40/EVND mode selection R40 EVND D12/STOPC mode selection D12 STOPC D13/INT0 mode selection D13 INT0
Note: * PMRC2 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRC2 is not reset but retains its value.
Figure 22 Port Mode Register C (PMRC)
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Timer mode register C2 (TMC2: $014) Bit Initial value Read/Write Bit name 3 -- -- 2 0 R/W 1 0 R/W TMC21 0 0 R/W TMC20
Not used TMC22
TMC22 0
TMC21 0
TMC20 0 1
R31/TOC mode selection R31 TOC TOC TOC -- R31 port Toggle output 0 output 1 output Inhibited
1
0 1
1
0
0 1
1
0 1 TOC PWM output
Figure 23 Timer Mode Register C2 (TMC2)
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Timer mode register D2 (TMD2: $015) Bit Initial value Read/Write Bit name 3 0 R/W TMD23 2 0 R/W TMD22 1 0 R/W TMD21 0 0 R/W TMD20
TMD23 0
TMD22 0
TMD21 0
TMD20 0 1
R32/TOD mode selection R32 TOD TOD TOD -- R32 port Toggle output 0 output 1 output Inhibited
1
0 1
1
0
0 1
1
0 1 TOD R32 PWM output Input capture (R32 port)
1 x : Don't care
x
x
x
Figure 24 Timer Mode Register D2 (TMD2)
Port mode register A (PMRA: $004) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 0 W 0 0 W
Not used Not used PMRA1 PMRA0
PMRA0 0 1 PMRA1 0 1
R43/SO1 mode selection R43 SO1 R42/SI1 mode selection R42 SI1
Figure 25 Port Mode Register A (PMRA)
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Serial mode register 1A (SM1A: $005) Bit Initial value Read/Write Bit name 3 0 W SM1A3 2 0 W SM1A2 1 0 W SM1A1 0 0 W SM1A0
SM1A3 0 1
R41/SCK1 mode selection R41 SCK1
SM1A2 0
SM1A1 0
SM1A0 0 1
SCK1 Output Output Output Output Output Output Output Input
Clock source Prescaler Prescaler Prescaler Prescaler Prescaler Prescaler System clock External clock
Prescaler division ratio / 2048 / 512 / 128 / 32 /8 /2 -- --
1
0 1
1
0
0 1
1
0 1
Figure 26 Serial Mode Register 1A (SM1A)
Compare enable register (CER: $018) Bit Initial value Read/Write Bit name 3 0 W CER3 2 -- -- Not used 1 0 W CER1 0 0 W CER0
CER3 0
Digital/Analog selection Digital input mode: RD0 /COMP0 and RD1 /COMP1 operate as an R port. Analog input mode: RD0 /COMP0 and RD 1 /COMP1 operate as analog input.
CER1 0 0 1 1
CER0 0 1 0 1
Analog input pin selection COMP0 COMP1 Not used Not used
1
Figure 27 Compare Enable Register
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Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name 3 0 W MIS3 2 0 W MIS2 1 -- -- 0 -- --
Not used Not used
MIS3 0 1
Pull-up MOS on/off selection Off On
MIS2 0 1
CMOS buffer on/off selection for pin R43/SO1 On Off
Figure 28 Miscellaneous Register (MIS)
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Prescalers
The MCU has the following prescaler S. The prescaler operating conditions are listed in table 22, and the prescaler output supply is shown in figure 29. The timers A, C, D input clocks except external events and the serial transmit clock except the external clock are selected from the prescaler outputs, depending on corresponding mode registers. Prescaler Operation Prescaler S: 11-bit counter that inputs a system clock signal. After being reset to $000 by MCU reset, prescaler S divides the system clock. Prescaler S keeps counting, except at MCU reset. Table 22
Prescaler Prescaler S
Prescaler Operating Conditions
Input Clock System clock Reset Condition MCU reset Stop Conditions MCU reset, stop mode
Timer A Timer C System clock Prescaler S Timer D Serial 1
Figure 29 Prescaler Output Supply
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Timers
The MCU has three timer/counters (A, C, and D). * Timer A: Free-running timer * Timer C: Multifunction timer * Timer D: Multifunction timer Timer A is an 8-bit free-running timer. Timers C and D are 8-bit multifunction timers, whose functions are listed in table 23. The operating modes are selected by software. Timer A Timer A Functions: Timer A has the following functions. * Free-running timer The block diagram of timer A is shown in figure 30. Timer A Operations: * Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA: $008). Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after reset to $00, and therefore it generates regular interrupts every 256 clocks. Registers for Timer A Operation: Timer A operating modes are set by the following registers. * Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A's operating mode and input clock source as shown in figure 31.
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Table 23
Functions Clock source Prescaler S External event Timer functions Free-running Event counter Reload Watchdog Input capture Timer outputs Toggle 0 output 1 output PWM Note: -- means not available.
Timer Functions
Timer A Available -- Available -- -- -- -- -- -- -- -- Timer C Available -- Available -- Available Available -- Available Available Available Available Timer D Available Available Available Available Available -- Available Available Available Available Available
Timer A interrupt request flag (IFTA)
Clock
Timer counter A (TCA) Overflow Internal data bus Timer mode register A (TMA)
Selector
/2 /4 /8 / 32 / 128 / 512 / 1024 / 2048
System clock
o PER
Prescaler S (PSS)
3
Figure 30 Block Diagram of Timer A
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Timer mode register A (TMA: $008) Bit Initial value Read/Write Bit name 3 -- -- Not used 2 0 W TMA2 1 0 W TMA1 0 0 W TMA0
Source Input clock TMA2 TMA1 TMA0 prescaler frequency Operating mode 0 0 0 1 1 0 1 1 0 0 1 1 0 1 PSS PSS PSS PSS PSS PSS PSS PSS 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc Timer A mode
Note: Timer counter overflow output period (seconds) = input clock period (seconds) x 256.
Figure 31 Timer Mode Register A (TMA)
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Timer C Timer C Functions: Timer C has the following functions. * Free-running/reload timer * Watchdog timer * Timer output operation (toggle, 0, 1, and PWM outputs) The block diagram of timer C is shown in figure 32.
System reset signal Watchdog on flag (WDON) Watchdog timer control logic
Timer C interrupt flag (IFTC)
TOC
Timer output control logic Timer read register CU (TRCU) Timer output control Timer read register CL (TRCL) Clock Timer counter C (TCC) Overflow
Selector
/2 /4 /8 /32 /128 /512 /1024 /2048
Timer write register CU (TWCU) Free-running /reload control 3 Timer mode register C1 (TMC1) Timer write register CL (TWCL)
System oPER clock
Prescaler S (PSS)
3 Timer mode register C2 (TMC2)
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Figure 32 Block Diagram of Timer C
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Timer C Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register C1 (TMC1: $00D). Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by software and incremented by one at each clock input. If an input clock is applied to timer C after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is initialized to its initial value set in timer write register C; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or MCU reset. Refer to figure 3 and table 1 for details. * Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing timer C by software before it reaches $FF. * Timer output operation: The following four output modes can be selected for timer C by setting timer mode register C2 (TMC2: $014). Toggle 0 output 1 output PWM output By selecting the timer output mode, pin R31/TOC is set to TOC. The output from TOC is reset low by MCU reset. Toggle output: When toggle output mode is selected, the output level is inverted if a clock is input after timer C has reached $FF. By using this function and reload timer function, clock signals can be output at a required frequency for the buzzer. The output waveform is shown in figure 33. PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output function. The output waveform differs depending on the contents of timer mode register C1 (TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is shown in figure 33. 0 output: When 0 output mode is selected, the output level is pulled low if a clock is input after timer C has reached $FF. Note that this function must be used only when the output level is high. 1 output: When 1 output mode is selected, the output level is set high if a clock is input after timer C has reached $FF. Note that this function must be used only when the output level is low.
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Toggle output waveform (timers C, and D) Free-running timer
256 clock cycles Reload timer
256 clock cycles
(256 - N) clock cycles (256 - N) clock cycles
PWM output waveform (timers C and D) T x (N + 1)
TMC13 = 0 TMD13 = 0 T x 256
T TMC13 = 1 TMD13 = 1
T x (256 - N) Notes: The waveform is always fixed low when N = $FF. T: Input clock period to counter (figures 34 and 41) N: The value of the timer write register
Figure 33 Timer Output Waveform
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Registers for Timer C Operation: By using the following registers, timer C operation modes are selected and the timer C count is read and written. Timer mode register C1 (TMC1: $00D) Timer mode register C2 (TMC2: $014) Timer write register C (TWCL: $00E, TWCU: $00F) Timer read register C (TRCL: $00E, TRCU: $00F) * Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the freerunning/reload timer function, input clock source, and the prescaler division ratio as shown in figure 34. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register C1 write instruction. Setting timer C's initialization by writing to timer write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid.
Timer mode register C1 (TMC1: $00D) Bit Initial value Read/Write Bit name 3 0 W TMC13 2 0 W TMC12 1 0 W TMC11 0 0 W TMC10
TMC13 0 1
Free-running/reload timer selection Free-running timer Reload timer
TMC12 0
TMC11 0
TMC10 0 1
Input clock period 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc
1
0 1
1
0
0 1
1
0 1
Figure 34 Timer Mode Register C1 (TMC1)
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* Timer mode register C2 (TMC2: $014): Three-bit read/write register that selects the timer C output mode as shown in figure 35. It is reset to $0 by MCU reset.
Timer mode register C2 (TMC2: $014) Bit Initial value Read/Write Bit name 3 -- -- 2 0 R/W 1 0 R/W TMC21 TMC21 0 0 0 R/W TMC20 TMC20 0 1 1 0 1 1 0 0 1 1 0 1 TOC PWM output R31/TOC mode selection R31 TOC TOC TOC -- R31 port Toggle output 0 output 1 output Inhibited
Not used TMC22 TMC22 0
Figure 35 Timer Mode Register C2 (TMC2) * Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of a lower digit (TWCL) and an upper digit (TWCU) as shown in figures 36 and 37. The lower digit is reset to $0 by MCU reset, but the upper digit value is invalid. Timer C is initialized by writing to timer write register C (TWCL: $00E, TWCU: $00F). In this case, the lower digit (TWCL) must be written to first, but writing only to the lower digit does not change the timer C value. Timer C is initialized to the value in timer write register C at the same time the upper digit (TWCU) is written to. When timer write register C is written to again and if the lower digit value needs no change, writing only to the upper digit initializes timer C.
Timer write register C (lower digit) (TWCL: $00E) Bit Initial value Read/Write Bit name 3 0 W TWCL3 2 0 W TWCL2 1 0 W TWCL1 0 0 W TWCL0
Figure 36 Timer Write Register C Lower Digit (TWCL)
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Timer write register C (upper digit) (TWCU: $00F) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined W TWCU3 W TWCU2 W TWCU1 W TWCU0
Figure 37 Timer Write Register C Upper Digit (TWCU) * Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of a lower digit (TRCL) and an upper digit (TRCU) that holds the count of the timer C upper digit as shown in figures 38 and 39. The upper digit (TRCU) must be read first. At this time, the count of the timer C upper digit is obtained, and the count of the timer C lower digit is latched to the lower digit (TRCL). After this, by reading TRCL, the count of timer C when TRCU is read can be obtained.
Timer read register C (lower digit) (TRCL: $00E) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRCL3 R TRCL2 R TRCL1 R TRCL0
Figure 38 Timer Read Register C Lower Digit (TRCL)
Timer read register C (upper digit) (TRCU: $00F) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRCU3 R TRCU2 R TRCU1 R TRCU0
Figure 39 Timer Read Register C Upper Digit (TRCU)
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Timer D Timer D Functions: Timer D has the following functions. * * * * Free-running/reload timer External event counter Timer output operation (toggle, 0, 1, and PWM outputs) Input capture timer
The block diagram for each operation mode of timer D is shown in figures 40-1 and 40-2. Timer D Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register D1 (TMD1: $010). Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by software and incremented by one at each clock input. If an input clock is applied to timer D after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is initialized to its initial value set in timer write register D; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer D interrupt request flag (IFTD: $003, bit 0). IFTD is reset by software or MCU reset. Refer to figure 3 and table 1 for details. * External event counter operation: Timer D is used as an external event counter by selecting the external event input as an input clock source. In this case, pin R40/EVND must be set to EVND by port mode register C (PMRC: $025). Either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2t cyc or longer. Timer D is incremented by one at each detection edge selected by detection edge select register 2 (ESR2: $027). The other operation is basically the same as the free-running/reload timer operation. * Timer output operation: The following four output modes can be selected for timer D by setting timer mode register D2 (TMD2: $015). Toggle 0 output 1 output PWM output By selecting the timer output mode, pin R32/TOD is set to TOD. The output from TOD is reset low by MCU reset. Toggle output: The operation is basically the same as that of timer-C's toggle output. 0 output: The operation is basically the same as that of timer-C's 0 output. 1 output: The operation is basically the same as that of timer-C's 1 output.
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PWM output: The operation is basically the same as that of timer-C's PWM output. * Input capture timer operation: The input capture timer counts the clock cycles between trigger edges input to pin EVND. Either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (ESR2: $027). When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL: $011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0. By selecting the input capture operation, pin R3 2/TOD is set to R3 2 and timer D is reset to $00.
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Timer D interrupt request flag (IFTD) TOD Timer output control logic
Timer read register DU (TRDU)
Timer output control Timer read register DL (TRDL) Clock Timer counter D (TCD) Overflow
Selector EVND Edge detection logic oPER
/2048
/2 /4 /8 /32 /128 /512
Free-running/ reload control 3
Timer write register DL (TWDL)
System clock
Prescaler S (PSS)
Timer mode register D1 (TMD1) 3 Timer mode register D2 (TMD2) Edge detection control
2 Edge detection selection register 2 (ESR2)
Figure 40-1 Block Diagram of Timer D (Free-Running/Reload Timer)
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Internal data bus
Timer write register DU (TWDU)
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Input capture status flag (ICSF) Input capture error flag (ICEF) Error control logic Timer D interrupt request flag (IFTD)
Timer read register DU (TRDU) Timer read register DL (TRDL) EVND Edge detection logic Read signal Clock Input capture timer control Internal data bus 57 Timer counter D (TCD) Overflow
Selector
3 Timer mode register D1 (TMD1)
System clock
oPER Prescaler S (PSS) Timer mode register D2 (TMD2) Edge detection control 2 Edge detection selection register 2 (ESR2)
Figure 40-2 Block Diagram of Timer D (in Input Capture Timer Mode)
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Registers for Timer D Operation: By using the following registers, timer D operation modes are selected and the timer D count is read and written. Timer mode register D1 (TMD1: $010) Timer mode register D2 (TMD2: $015) Timer write register D (TWDL: $011, TWDU: $012) Timer read register D (TRDL: $011, TRDU: $012) Port mode register C (PMRC: $025) Detection edge select register 2 (ESR2: $027) * Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the freerunning/reload timer function, input clock source, and the prescaler division ratio as shown in figure 41. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D's initialization by writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change becomes valid. When selecting the input capture timer operation, select the internal clock as the input clock source.
Timer mode register D1 (TMD1: $010) Bit Initial value Read/Write Bit name 3 0 W TMD13 2 0 W TMD12 1 0 W TMD11 0 0 W TMD10
TMD13 0 1
Free-running/reload timer selection Free-running timer Reload timer
TMD12 0
TMD11 0
TMD10 0 1
Input clock period and input clock source 2048tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc R40/EVND (external event input)
1
0 1
1
0
0 1
1
0 1
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Figure 41 Timer Mode Register D1 (TMD1)
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* Timer mode register D2 (TMD2: $015): Four-bit read/write register that selects the timer D output mode and input capture operation as shown in figure 42. It is reset to $0 by MCU reset.
Timer mode register D2 (TMD2: $015) Bit Initial value Read/Write Bit name 3 0 R/W TMD23 2 0 R/W TMD22 1 0 R/W TMD21 0 0 R/W TMD20
TMD23 0
TMD22 0
TMD21 0
TMD20 0 1
R32/TOD mode selection R32 TOD TOD TOD -- R32 port Toggle output 0 output 1 output Inhibited
1
0 1
1
0
0 1
1 x x
0 1 TOD R32 PWM output Input capture (R32 port)
1 x : Don't care
x
Figure 42 Timer Mode Register D2 (TMD2) * Timer write register D (TWDL: $011, TWDU: $012): Write-only register consisting of a lower digit (TWDL) and an upper digit (TWDU) as shown in figures 43 and 44. The operation of timer write register D is basically the same as that of timer write register C (TWCL: $00E, TWCU: $00F).
Timer write register D (lower digit) (TWDL: $011) Bit Initial value Read/Write Bit name 3 0 W TWDL3 2 0 W TWDL2 1 0 W TWDL1 0 0 W TWDL0
Figure 43 Timer Write Register D Lower Digit (TWDL)
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Timer write register D (upper digit) (TWDU: $012) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined W TWDU3 W TWDU2 W TWDU1 W TWDU0
Figure 44 Timer Write Register D Upper Digit (TWDU) * Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of a lower digit (TRDL) and an upper digit (TRDU) as shown in figures 45 and 46. The operation of timer read register D is basically the same as that of timer read register C (TRCL: $00E, TRCU: $00F). When the input capture timer operation is selected and if the count of timer D is read after a trigger is input, either the lower or upper digit can be read first.
Timer read register D (lower digit) (TRDL: $011) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRDL3 R TRDL2 R TRDL1 R TRDL0
Figure 45 Timer Read Register D Lower Digit (TRDL)
Timer read register D (upper digit) (TRDU: $012) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRDU3 R TRDU2 R TRDU1 R TRDU0
Figure 46 Timer Read Register D Upper Digit (TRDU)
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* Port mode register C (PMRC: $025): Write-only register that selects R40/EVND pin function as shown in figure 47. It is reset to $0 by MCU reset.
Port mode register C (PMRC: $025) Bit Initial value Read/Write Bit name 3 0 W PMRC3 2 0 W 1 0 W 0 -- --
PMRC2 PMRC1 Not used
PMRC1 0 1 PMRC2 0 1 PMRC3 0 1
R40/EVND mode selection R40 EVND D12/STOPC mode selection D12 STOPC D13/INT0 mode selection D13 INT0
Figure 47 Port Mode Register C (PMRC) * Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of signals input to pin EVND as shown in figure 48. It is reset to $0 by MCU reset.
Detection edge register 2 (ESR2: $027) Bit Initial value Read/Write Bit name 3 0 W ESR23 2 0 W 1 -- -- 0 -- --
ESR22 Not used Not used
ESR23 0
ESR22 0 1
EVND detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection *
1
0 1
Note: * Both falling and rising edges are detected.
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Detection Edge Select Register 2 (ESR2)
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Notes on Use
When using the timer output as PWM output, note the following point. From the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 24. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle. Table 24 PWM Output Following Update of Timer Write Register
PWM Output Mode Free running Timer Write Register is Updated during High PWM Output
Timer write register updated to value N
Timer Write Register is Updated during Low PWM Output
Timer write register updated to value N
Interrupt request
Interrupt request
T x (255 - N) T x (N + 1)
T x (N' + 1) T x (255 - N) T x (N + 1)
Reload
Timer write register updated to value N
Interrupt request
Timer write register updated to value N
Interrupt request
T
T x (255 - N)
T
T T x (255 - N) T
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Serial Interface 1
The MCU has one channel of serial interface. The serial interface serially transfers or receives 8-bit data, and includes the following features. * Multiple transmit clock sources External clock Internal prescaler output clock System clock * Output level control in idle states Serial interface 1 * * * * * * * Serial data register 1 (SR1L: $006, SR1U: $007) Serial mode register 1A (SM1A: $005) Serial mode register 1B (SM1B: $028) Port mode register A (PMRA: $004) Miscellaneous register (MIS: $00C) Octal counter (OC) Selector
The block diagram of serial interface 1 is shown in figure 49.
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Octal counter (OC)
Serial interrupt request flag (IFS1)
SO1
Idle control logic Serial data register (SR1L/U) Clock Transfer control 1/2 1/2 Internal data bus
SCK1
I/O control logic
SI1
Selector
Selector
3 Serial mode register 1A (SM1A)
System clock
oPER
/2 /8 /32 /128 /512 /2048 Prescaler S (PSS)
Serial mode register 1B (SM1B)
Figure 49 Block Diagram of Serial Interface 1
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Serial Interface Operation Selecting and Changing the Operating Mode: Table 25 lists the serial interface's operating modes. To select an operating mode, use one of these combinations of port mode register A (PMRA: $004), and serial mode register 1A (SM1A: $005) settings; to change the operating mode of serial interface 1, always initialize the serial interface internally by writing data to serial mode register 1A. Note that serial interface 1 is initialized by writing data to serial mode register 1A. Refer to the following section Registers for Serial Interface for details. Pin Setting: The R41/SCK 1 pin is controlled by writing data to serial mode register 1A (SM1A: $005). Pins R42/SI 1 and R4 3/SO 1 are controlled by writing data to port mode register A (PMRA: $004). Refer to the following section Registers for Serial Interface for details. Transmit Clock Source Setting: The transmit clock source of serial interface 1 is set by writing data to serial mode register 1A (SM1A: $005) and serial mode register 1B (SM1B: $028). Refer to the following section Registers for Serial Interface for details. Data Setting: Transmit data of serial interface 1 is set by writing data to serial data register 1 (SR1L: $006, SR1U: $007). Receive data of serial interface 1 is obtained by reading the contents of serial data register 1. The serial data is shifted by the transmit clock and is input from or output to an external system. The output level of the SO1 pin is invalid until the first data is output after MCU reset, or until the output level control in idle states is performed. Transfer Control: Serial interface 1 is activated by the STS instruction. The octal counter is reset to 000 by the STS instruction, and it increments at the rising edge of the transmit clock for serial interface. When the eighth transmit clock signal is input or when serial transmission/reception is discontinued, the octal counter is reset to 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) for serial interface 1 is set, and the transfer stops. When the prescaler output is selected as the transmit clock of serial interface 1, the transmit clock frequency is selected as 4t cyc to 8192tcyc by setting bits 0 to 2 (SM1A0-SM1A2) of serial mode register 1A (SM1A: $005) and bit 0 (SM1B0) of serial mode register 1B (SM1B: $028) as listed in table 26. Table 25
SM1A Bit 3 1
Serial Interface 1 Operating Modes
PMRA Bit 1 0 Bit 0 0 1 1 0 1 Operating Mode Continuous clock output mode Transmit mode Receive mode Transmit/receive mode
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Table 26
SM1B Bit 0 0
Serial Transmit Clock (prescaler output)
SM1A Bit 2 0 Bit 1 0 Bit 0 0 1 1 0 1 1 0 0 1 Prescaler Division Ratio / 2048 / 512 / 128 / 32 /8 /2 / 4096 / 1024 / 256 / 64 / 16 /4 Tranamit Clock Frequency 4096t cyc 1024t cyc 256t cyc 64t cyc 16t cyc 4t cyc 8192t cyc 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc
1
0
0
0 1
1
0 1
1
0
0 1
Operating States: Serial interface 1 has the following operating states; transitions between them are shown in figure 50. STS wait state Transmit clock wait state Transfer state Continuous transmit clock output state (only in internal clock mode)
* STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 50). In STS wait state, serial interface 1 is initialized and the transmit clock is ignored. If the STS instruction is then executed (01, 11), serial interface 1 enters transmit clock wait state. * Transmit clock wait state: Transmit clock wait state is between the STS execution and the falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments the octal counter, shifts serial data register 1 (SR1L: $006, SR1U: $007), and enters the serial interface in transfer state. However, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). The serial interface enters STS wait state by writing data to serial mode register 1A (SM1A: $005) (04, 14) in transmit clock wait state. * Transfer state: Transfer state is between the falling edge of the first clock and the rising edge of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In internal clock mode, the www..com transmit clock stops after outputting eight clocks.
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In transfer state, writing data to serial mode register 1A (SM1A: $005) (06, 16) initializes serial interface 1, and STS wait state is entered. If the state changes from transfer to another state, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set by the octal counter that is reset to 000. * Continuous clock output state (only in internal clock mode): Continuous clock output state is entered only in internal clock mode. In this state, the serial interface does not transmit/receive data but only outputs the transmit clock from the SCK 1 pin. When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. If serial mode register 1A (SM1A: $005) is written to in continuous clock output mode (18), STS wait state is entered.
External clock mode
STS wait state (Octal counter = 000, transmit clock disabled)
00 MCU reset
SM1A write 04 01 STS instruction 02 Transmit clock Transmit clock wait state (Octal counter = 000) 03 8 transmit clocks Internal clock mode SM1A write 18 Continuous transmit clock output state (PMRA 0, 1 = 0, 0) Transmit clock 17 12 Transmit clock Transmit clock wait state (Octal counter = 000)
06 SM1A write (IFS1 1)
Transfer state (Octal counter 000)
05 STS instruction (IFS1 1)
STS wait state (Octal counter = 000, transmit clock disabled)
10 MCU reset
SM1A write 14
13 8 transmit clocks 11 STS instruction 16 SM1A write (IFS1 1)
Transfer state (Octal counter 000) 15 STS instruction (IFS1 1)
Note: Refer to the Operating States section for the corresponding encircled numbers.
Figure 50 Serial Interface State Transitions Output Level Control in Idle States: When serial interface 1 is in STS instruction wait state, the output of serial output pin, SO1 can be controlled by setting bit 1 (SM1B1) of serial mode register 1B (SM1B: $028) to 0 or 1. The output level control example of serial interface 1 is shown in Figure 51. Note that the output level cannot be controlled in transfer state.
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Transmit clock wait state State STS wait state Transfer state MCU reset Port selection PMRA write SM1A write SM1B write External clock selection Output level control in idle states Data write for transmission SR1L, SR1U write STS instruction SCK1 pin (input) SO1 pin Undefined LSB IFS1 External clock mode Transmit clock wait state State STS wait state Transfer state MCU reset Port selection PMRA write SM1A write SM1B write Internal clock selection Output level control in idle states Data write for transmission SR1L, SR1U write STS instruction SCK1 pin (output) SO1 pin Undefined LSB IFS1 Internal clock mode
Transmit clock wait state STS wait state
Dummy write for state transition Output level control in idle states
MSB
Flag reset at transfer completion
STS wait state
Output level control in idle states
MSB
Flag reset at transfer completion
Figure 51 Example of Serial Interface 1 Operation Sequence
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Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit clock error of this type can be detected as shown in figure 52. If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is entered. After the transfer is completed and IFS is reset, writing to serial mode register 1A (SM1A: $005) changes the state from transfer to STS wait. At this time serial interface 1 is in the transfer state, and the serial 1 interrupt request flag is set again, and therefore the error can be detected. Notes on Use: * Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode register 1A (SM1A: $005) again. * Serial 1 interrupt request flag (IFS1: $003, bit 2) set: For serial interface 1, if the state is changed from transfer state to another by writing to serial mode register 1A (SM1A: $005) or executing the STS instruction during the first low pulse of the transmit clock, the serial 1 interrupt request flag is not set. To set the serial 1 interrupt request flag, a serial mode register 1A write or STS instruction execution must be programmed to be executed after confirming that the SCK 1 pin is at 1, that is, after executing the input instruction to port R4.
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Transmit clock wait state State SCK 1 pin (input) Noise 1 2 3 4 SM1A write IFS1
Transfer completion (IFS1 1)
Interrupts inhibited
IFS1 0
SM1A write
IFS1 = 1
Yes
Transmit clock error processing
No
Normal termination
Transmit clock error detection flowchart
Transmit clock wait state Transfer state
Transfer state
5
6
7 8 Transfer state has been entered by the transmit clock error. When SM1A is written, IFS1 is set.
Flag set because octal counter reaches 000. Transmit clock error detection procedures
Flag reset at transfer completion.
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Figure 52 Transmit Clock Error Detection
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Registers for Serial Interface The serial interface operation is selected, and serial data is read and written by the following registers. * * * * * Serial mode register 1A (SM1A: $005) Serial mode register 1B (SM1B: $028) Serial data register 1 (SR1L: $006, SR1U: $007) Port mode register A (PMRA: $004) Miscellaneous register (MIS: $00C)
Serial Mode Register 1A (SM1A: $005): This register has the following functions (figure 53). * * * * R4 1/SCK 1 pin function selection Serial interface 1 transmit clock selection Serial interface 1 prescaler division ratio selection Serial interface 1 initialization
Serial mode register 1A (SM1A: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset. A write signal input to serial mode register 1A (SM1A: $005) discontinues the input of the transmit clock to serial data register 1 (SR1L: $006, SR1U: $007) and the octal counter, and the octal counter is reset to 000. Therefore, if a write is performed during data transfer, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set. Written data is valid from the second instruction execution cycle after the write operation, so the STS instruction must be executed at least two cycles after that.
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Serial mode register 1A (SM1A: $005) Bit Initial value Read/Write Bit name 3 0 W SM1A3 2 0 W SM1A2 1 0 W SM1A1 0 0 W SM1A0
SM1A3 0 1
R41/SCK1 mode selection R41 SCK1
SM1A2 0
SM1A1 0
SM1A0 0 1
SCK1 Output
Clock source Prescaler
Prescaler division ratio Refer to table 26
1
0 1
1
0
0 1
1
0 1
Output Input
System clock External clock
-- --
Figure 53 Serial Mode Register 1A (SM1A) Serial Mode Register 1B (SM1B: $028): This register has the following functions (figure 54). * Serial interface 1 prescaler division ratio selection * Serial interface 1 output level control in idle states Serial mode register 1B (SM1B: $028) is a 2-bit write-only register. It cannot be written during data transfer. By setting bit 0 (SM1B0) of this register, the serial interface 1 prescaler division ratio is selected. Only bit 0 (SM1B0) can be reset to 0 by MCU reset. By setting bit 1 (SM1B1), the output level of the SO1 pin is controlled in idle states of serial interface 1. The output level changes at the same time that SM1B1 is written to.
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Serial mode register 1B (SM1B: $028) Bit Initial value Read/Write Bit name 3 -- -- 2 -- --
1 Undefined W
0 0 W SM1B0
Not used Not used SM1B1
SM1B1 0 1
Output level control in idle states Low level High level
SM1B0 0 1
Serial clock division ratio Prescaler output divided by 2 Prescaler output divided by 4
Figure 54 Serial Mode Register 1B (SM1B) Serial Data Register 1 (SR1L: $006, SR1U: $007): This register has the following functions (figures 55 and 56) * Serial interface 1 transmission data write and shift * Serial interface 1 receive data shift and read Writing data in this register is output from the SO1 pin, LSB first, synchronously with the falling edge of the transmit clock; data is input, LSB first, through the SI1 pin at the rising edge of the transmit clock. Input/output timing is shown in figure 57. Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed.
Serial data register 1(lower digit) (SR1L: $006) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R/W SR13 R/W SR12 R/W SR11 R/W SR10
Figure 55 Serial Data Register 1 (SR1L)
Serial data register 1(upper digit) (SR1U: $007) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R/W SR17 R/W SR16 R/W SR15 R/W SR14
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Figure 56 Serial Data Register 1 (SR1U)
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Transmit clock 1 Serial output data LSB 2 3 4 5 6 7 8 MSB
Serial input data latch timing
Figure 57 Serial Interface Output Timing Port Mode Register A (PMRA: $004): This register has the following functions (figure 58). * R4 2/SI 1 pin function selection * R4 3/SO 1 pin function selection Port mode register A (PMRA: $004) is a 2-bit write-only register, and is reset to $0 by MCU reset.
Port mode register A (PMRA: $004) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 0 W 0 0 W
Not used Not used PMRA1 PMRA0 PMRA0 0 1 PMRA1 0 1 R43/SO1 mode selection R43 SO1 R42/SI1 mode selection R42 SI1
Figure 58 Port Mode Register A (PMRA)
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Miscellaneous Register (MIS: $00C): This register has the following functions (figure 59). * R4 3/SO 1 pin PMOS control Miscellaneous register (MIS: $00C) is a 2-bit write-only register and is reset to $0 by MCU reset.
Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name 3 0 W MIS3 2 0 W MIS2 1 -- -- 0 -- --
Not used Not used MIS2 0 1 MIS3 0 1 R43/SO1 PMOS on/off selection On Off Pull-up MOS on/off selection Off On
Figure 59 Miscellaneous Register (MIS)
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Comparator
The block diagram of the comparator is shown in figure 60. The comparator compares input voltage with the reference voltage. Setting 1 to bit 3 (CER3) of the compare enable register (CER: $018) executes a voltage comparison. When an input voltage at COMP0, COMP1 is higher than the reference voltage, the TM or TMD command sets the status flag (ST) high for the corresponding bits of the compare data register (CDR: $017) to COMP 0 and COMP1. On the other hand, when an input voltage at COMP0, COMP1 is lower, the TM or TMD command clears the ST to 0.
COMP0 COMP1
Selector
+ -
Comparator
Comparator data register (CDR) Internal data bus Comparator enable register (CER)
VCref
Figure 60 Block Diagram of Comparator
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Compare Enable Register (CER: $018): Three-bit write-only register which enables comparator operation, and selects the reference voltage and the analog input pin (figure 61).
Compare enable register (CER: $018) Bit Initial value Read/Write Bit name 3 0 W CER3 2 -- -- 1 0 W 0 0 W CER0
Not used CER1
CER3 0
Digital/Analog selection Digital input mode: RD0 /COMP0, RD1 /COMP1 operate as R port Analog input mode: RD0 /COMP0, RD1 /COMP1 operate as analog input
CER1 0
CER0 0 1
Analog input pin selection COMP0 COMP1 Not used Not used
1
1
0 1
Figure 61 Compare Enable Register Compare Data Register (CDR: $017): Two-bit read-only register which latches the result of the comparison between the analog input pins and the reference voltage. Bits 0 and 1 corresponds the results of comparison with COMP0 and COMP1, respectively. This register can be read only by the TM or TMD command. Only bit CER3 corresponds to the analog input pin which the input pin selection is made through pins CER0 and CER1. After a compare operation, the data in this register is not retained (figure 62).
Compare data register (CDR: $017) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 R CDR1 0 R CDR0 Result of COMP0 comparison Result of COMP1 comparison
Undefined Undefined
Not used Not used
Figure 62 Compare Data Register Note on Use: During the compare operation pins RD0/COMP0 and RD1/COMP1 operate as analog inputs and cannot operate as R ports. The comparator can operate in active mode but is disabled in other modes. RE0/VC ref cannot operate www..comas an R port when the external input voltage is selected as the reference.
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Programmable ROM (HD4074054, HD4074094)
The HD4074054 and HD4074094 are ZTATTM microcomputers with built-in PROM that can be programmed in PROM mode. PROM Mode Pin Description
Pin No. DP-42S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FP-44A 39 40 41 42 43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 MCU Mode Pin Name RD0/COMP0 RD1/COMP1 RD2 RD3 RC0 RE 0/VCref TEST OSC 1 OSC 2 RESET GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D12/STOPC D13/INT0 R0 0/INT1 R1 0 R1 1 R1 2 I/O I I I I I I I I O I I I/O I/O I/O I/O I/O* I/O* I/O* I/O* I/O I/O I I I/O I/O I/O I/O VCC VCC O4 O5 O6 O7 A13 A14 A9 VPP M0 A5 A6 A7 I I I I I/O I/O I/O I/O I I I RESET GND O O I M1 TEST VCC I I PROM Mode Pin Name CE OE I/O I I
Note: I/O: Input/output pin, I: Input pin, O: Output pin * HD404054 Series: I/O, HD404094 Series: O
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Pin No. DP-42S 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 - - FP-44A 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 22 44 MCU Mode Pin Name R1 3 R2 0 R2 1 R2 2 R2 3 R3 0 R3 1/TOC R3 2/TOD R3 3 R4 0/EVND R4 1/SCK 1 R4 2/SI1 R4 3/SO 1 SEL VCC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I - - VCC PROM Mode Pin Name A8 A0 A10 A11 A12 A1 A2 A3 A4 O0 O1 O2 O3 I/O I I I I I I I I I I/O I/O I/O I/O
Note: I/O: Input/output pin, I: Input pin, O: Output pin
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Programming the Built-In PROM
The MCU's built-in PROM is programmed in PROM mode. PROM mode is set by pulling TEST, M0, and M1 low, and RESET low as shown in figure 63. In PROM mode, the MCU does not operate, but it can be programmed in the same way as any other commercial 27256-type EPROM using a standard PROM programmer and an 42-to-28-pin socket adapter. Recommended PROM programmers and socket adapters of the HD4074054 and HD4074094 are listed in table 27. Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion circuit to enable the use of a general-purpose PROM programmer. This circuit splits each instruction into five lower bits and five upper bits that are read from or written to consecutive addresses. This means that if, for example, 4-kwords of built-in PROM are to be programmed by a general-purpose PROM programmer, a 8-kbyte address space ($0000-$7FFF) must be specified.
VCC
RESET TEST M0 M1
VCC
VPP
O0 to O7 VPP VCC OSC1 D2 D3 HD4074054 HD4074094 A0 to A14
Data O0 to O7
Address A0 to A14
OE CE
OE CE
GND
Figure 63 PROM Mode Connections Table 27 Recommended PROM Programmers and Socket Adapters
Socket Adapter Model Name 121B PKW-1000 Package DP-42S FP-44A Model Name HS4654ESS01H HS4654ESH01H Manufacturer Hitachi Hitachi
PROM Programmer Manufacturer DATA I/O Corp. AVAL Corp.
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Warnings 1. Always specify addresses $0000 to $1FFF when programming with a PROM programmer. If address $2000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in unused addresses to $FF. Note that the plastic-package version cannot be erased or reprogrammed. 2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1 positions match), otherwise overcurrents may damage the LSI. Before starting programming, make sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the programmer. 3. PROM programmers have two voltages (VPP ): 12.5 V and 21 V. Remember that ZTATTM devices require a VPP of 12.5 V--the 21-V setting will damage them. 12.5 V is the Intel 27256 setting. Programming and Verification The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage to data reliability. Programming and verification modes are selected as listed in table 28. Table 28 PROM Mode Selection
Pin Mode Programming Verification Programming inhibited CE Low High High OE High Low High VPP VPP VPP VPP O0-O7 Data input Data output High impedance
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Addressing Modes
RAM Addressing Modes The MCU has three RAM addressing modes, as shown in figure 64 and described below.
W register W1 W0 X3 X register X2 X1 X0 Y3 Y register Y2 Y 1 Y0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Register direct addressing
1st word of Instruction Opcode d
9
2nd word of Instruction d8 d7 d6 d5 d4 d3 d2 d1 d0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Direct addressing
Instruction Opcode 0 0 0 1 0 0 m3 m2 m1 m0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Memory register addressing
Figure 64 RAM Addressing Modes Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions.
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ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 65 and described below. Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC 13-PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC7-PC0) with eight-bit immediate data. If the BR instruction is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next physical page, as shown in figure 67. This means that the execution of the BR instruction on a page boundary will make the program branch to the next page. Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000- $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC 5-PC0), and 0s are placed in the eight highorder bits (PC13-PC6). Table Data Addressing Mode: A program can branch to an address determined by the contents of fourbit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction as shown in figure 66. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter.
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[JMPL] [BRL] [CALL] 1st word of instruction Opcode p3 p2 p1 p0 d9 d8 2nd word of instruction d7 d6 d5 d4 d3 d2 d1 d0
Program counter
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct addressing Instruction [BR] Opcode b7 b6 b5 b4 b3 b2 b1 b0
Program counter
PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current page addressing Instruction [CAL] 0 0 0 0 0 Opcode 0 0 0 d5 d4 d3 d2 d1 d0
Program counter
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero page addressing Instruction
[TBR]
Opcode
p3
p2
p1
p0 B register B3 B2 B1 B0 A3 Accumulator A2 A1 A0
0 Program counter
0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Table data addressing
Figure 65 ROM Addressing Modes
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Instruction [P] Opcode p3 p2 p1 p0 B3 0 0 B register B2 B1 B0 A3 Accumulator A2 A1 A0
Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address designation ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Accumulator, B register
B3
B2
B1
B0
A3 A
2
A1
A
0
If RO 8 = 1
ROM data
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Output registers R1, R2
R23 R22 R21 R20 R13 R12 R11 R10 Pattern output
If RO 9 = 1
Figure 66 P Instruction
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256 (n - 1) + 255 BR AAA 256n
AAA
NOP
BR BR
AAA BBB
256n + 254 256n + 255 256 (n + 1)
BBB
NOP
Figure 67 Branching when the Branch Destination is on a Page Boundary
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Absolute Maximum Ratings
Item Supply voltage Programming voltage Pin voltage Symbol VCC VPP VT Io -Io Io Value -0.3 to +7.0 -0.3 to +14.0 Unit V V 1 Notes
-0.3 to VCC + 0.3 V -0.3 to +15.0 V mA mA mA mA mA mA C C 2 3 4 5, 6 5, 7 8, 9 8, 10
Total permissible input current Total permissible output current Maximum input current
80 50 4 30
Maximum output current
-I o
4 20
Operating temperature Storage temperature
Topr Tstg
-20 to +75 -55 to +125
Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to D 13 (VPP) of HD4074054 and HD4074094. 2. Applies to D 4 to D7 of HD404092, HD404094, and HD4074094. 3. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to GND. 4. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 5. The maximum input current is the maximum current flowing from each I/O pin to GND. 6. Applies to D 0-D 3, and R0-R4. 7. Applies to D 4-D 9 . 8. The maximum output current is the maximum current flowing out from V CC to each I/O pin. 9. Applies to D 4-D 9 and R0-R4. 10. Applies to D 0-D 3.
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Electrical Characteristics
DC Characteristics (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V to 6.0 V, GND = 0 V, T a = -20 C to +75C; HD40A4052, HD40A4054: VCC = 4.0 V to 6.0 V, GND = 0 V, T a = -20C to +75C; HD4074054, HD4074094: VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified)
Item Input high voltage Symbol VIH Pin(s) Min Typ -- Max Unit Test Condition Notes
RESET, STOPC, 0.9 VCC INT0, INT1, SCK 1, SI 1, EVND OSC 1 RESET, STOPC, -0.3 INT0, INT1, SCK 1, SI 1, EVND OSC 1 -0.3 SCK 1, SO1, TOC,TOD SCK 1, SO1, TOC,TOD
VCC + 0.3 V
VCC - 0.3 -- --
VCC + 0.3 V 0.10 VCC V
External clock
Input low voltage
VIL
--
0.3 -- 0.4 1
V V V A
External clock -I OH = 0.5 mA I OL = 0.4 mA Vin = 0 V to VCC 1
Output high voltage Output low voltage I/O leakage current
VOH VOL | IIL |
VCC - 1.0 -- -- -- --
RESET, STOPC, -- INT0, INT1, SCK 1, SI 1, SO1, EVND, OSC 1, TOC, TOD VCC --
Current dissipation in active mode
I CC1
5
--
mA
VCC = 5 V, f OSC = 4 MHz Digital input mode VCC = 5 V, f OSC = 8 MHz Digital input mode VCC = 3 V, f OSC = 800 kHz Digital input mode
2, 4,
--
5
10
mA
3, 4,
I CC2
VCC
--
0.6
1.8
mA
2, 4,
I CMP1
VCC
--
9
--
mA
VCC = 5 V, 2, 4, f OSC = 4 MHz Analog comp. mode VCC = 5 V, 3, 4, f OSC = 8 MHz Analog comp. mode VCC = 3 V, 2, 4, f OSC = 800 kHz Analog comp. mode
--
9
15
mA
I CMP2
VCC
--
3.1
4.3
mA
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Item Symbol Pin(s) VCC Min -- -- I SBY2 Current dissipation I STOP in stop mode VCC VCC -- -- -- Stop mode retaining voltage Comparator input reference voltage scope Notes: 1. 2. 3. 4. VSTOP VC ref VCC VC ref -- 0 Typ 1.2 3 0.2 1 1 1.3 -- Max -- 6 0.7 5 10 -- Unit mA mA mA A A V Test Condition VCC = 5 V, f OSC = 4 MHz VCC = 5 V, f OSC = 8 MHz VCC = 3 V, f OSC = 800 kHz VCC = 3 V VCC = 5 V Notes 2, 6, 3, 6, 2, 6, 2, 7 3, 7 8 Current dissipation I SBY1 in standby mode
VCC - 1.2 V
5.
6.
7.
8.
Output buffer current is excluded. Applies to HD404052, HD404054, HD4074054, HD404092, HD404094 and HD4074094. Applies to HD40A4052 and HD40A4054. I CC1 and I CC2 are the source currents when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET at GND (0 V to 0.3V) TEST at V CC (VCC - 0.3 to VCC) RD0 and RD1 pins are analog input mode when no I/O current is flowing. Test conditions: MCU: Analog input mode Pins: RD0/COMP0 at GND (0 V to 0.3 V) RD1/COMP1 at GND (0 V to 0.3 V) RE 0/VCref at GND (0 V to 0.3 V) I SBY1 and I SBY2 are the source currents when no I/O current is flowing while the MCU timer is operating. Test conditions: MCU: I/O reset Serial interface stopped Standby mode Pins: RESET at V CC (VCC - 0.3 to VCC) TEST at V CC (VCC - 0.3 to VCC) These are the source currents when no I/O current is flowing. Test conditions: Pins: RESET at V CC (VCC - 0.3 to VCC) TEST at V CC (VCC - 0.3 to VCC) D13* at VCC (VCC - 0.3 to VCC) Note: * Applies to HD4074054 and HD4074094 RAM data retention.
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I/O Characteristics for Standard Pins (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V to 6.0 V, GND = 0 V, T a = -20C to +75C; HD40A4052, HD40A4054: V CC = 4.0 V to 6.0 V, GND = 0 V, T a = -20C to +75C; HD4074054, HD4074094: V CC = 2.7 V to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified)
Item Input high voltage Input low voltage Output high voltage Output low voltage I/O leakage current Symbol Pin(s) VIH VIL VOH VOL | IIL | Min Typ -- -- Max Unit Test Condition Notes
D12-D 13 , 0.7 VCC R0-RD, RE0 D12-D 13 , -0.3 R0-RD, RE0 R0-R4 R0-R4
VCC + 0.3 V 0.3 VCC -- 0.4 1 1 1 20 -- 500 V V V A A A A A A V V -I OH = 0.5 mA I OL = 0.4 mA Vin = 0 V to VCC Vin = 0 V to VCC 1 1, 2, 4
VCC - 1.0 -- -- -- -- -- -- -- 30 100
D12, R0-RD, -- RE 0 D13 -- -- --
Vin = VCC - 0.3 V to VCC 1, 3 Vin = 0 V to 0.3 V VCC = 3 V, Vin = 0 V VCC = 5 V, Vin = 0 V Analog compare mode Analog compare mode 1, 3 2, 3 4 5 5
Pull-up MOS -I PU current
R0-R4
-- 20
Input high voltage Input low voltage Notes: 1. 2. 3. 4. 5.
VIHA VILA
COMP0, COMP1 COMP0, COMP1
-- --
VC ref+0.0 -- 5 VC ref-0.05 --
Output buffer current is excluded. Applies to HD404052, HD404054, HD404092, HD404094. Applies to HD4074054, HD4074094. Applies to HD40A4052, HD40A4054. The analog input reference voltage should be in the range 0 VC ref VCC-1.2.
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I/O Characteristics for High-Current Pins and Intermediate-Voltage Pins (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V to 6.0 V, GND = 0 V, T a = -20C to +75C; HD40A4052, HD40A4054: VCC = 4.0 V to 6.0 V, GND = 0 V, T a = -20C to +75C; HD4074054, HD4074094: VCC = 2.7 V to 5.5 V, GND = 0 V, T a = -20C to +75C, unless otherwise specified)
Pin(s) Item Input high voltage Input low voltage Output high voltage Symbol VIH VIL VOH HD404054 HD404094 Series Series Min D0-D 9 D0-D 9 D0-D 9 D0-D 3 D0-D 3, D8, D9 D0-D 3, D8, D9 D0-D 3, D8, D9 D0-D 3 0.7 VCC -0.3 Typ -- -- Max VCC + 0.3 0.3 VCC -- -- Unit V V V V -I OH = 0.5 mA -I OH = 10 mA, VCC = 4.5 V to 6.0 V 500 k at 12 V I OL = 0.4 mA I OL = 15 mA, VCC = 4.5 V to 6.0 V 2 2 Test Condition Notes
VCC - 1.0 -- 2.0 --
-- Output low voltage VOL D0-D 9 D4-D 9
D4-D 7 D0-D 9 D4-D 9
11.5 -- --
-- -- --
-- 0.4 2.0
V V V
I/O leakage current
| IIL |
D0-D 9 --
D0-D 3, D8, D9 D4-D 7 D0-D 3 --
-- -- -- 20 -- 20
-- -- 30 100 30 100
1 20 -- 500 -- 500
A A A A A A
Vin = 0 V to VCC 1 Vin = 0 V to 12 V VCC = 3 V, Vin = 3 V VCC = 5 V, Vin = 5 V VCC = 3 V, Vin = 0 V VCC = 5 V, Vin = 0 V 1 3 4 3 4
Pull-down I PD MOS current
D0-D 3
Pull-up MOS -I PU current
D4-D 9
D8, D9 --
Notes: 1. 2. 3. 4.
Output buffer current is excluded. When using HD4074054, HD4074094, VCC = 4.5 V to 5.5 V. Applies to HD404052, HD404054, HD4074054, HD404092, HD404094, HD4074094. Applies to HD40A4052, HD40A4054.
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AC Characteristics (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V to 6.0 V, GND = 0 V, T a = -20 C to +75C; HD40A4052, HD40A4054: VCC = 4.0 V to 6.0 V, GND = 0 V, T a = -20C to +75C; HD4074054, HD4074094: VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified)
Item Clock oscillation frequency Symbol Pin(s) f OSC OSC 1, OSC 2 Min 0.4 0.4 Instruction cycle time t cyc -- -- -- -- Oscillation stabilization time (ceramic) t RC OSC 1, OSC 2 -- Typ -- -- 8 3.76 1 0.47 -- Max 4 8.5 -- -- -- -- 7.5 Unit MHz MHz s s s s ms f OSC = 4 MHz, /32 f OSC = 8.5 MHz, /32 f OSC = 4 MHz, /4 f OSC = 8.5 MHz, /4 Test Condition Notes 1 2 1, 4 2, 4 1, 3 2, 3
VCC = 2.7 V to 5.5 V: 3, 4 HD4074054, HD4074094 VCC = 2.7 V to 6.0 V: HD404052, HD404054, HD404092, HD404094
--
--
60
ms
VCC = 1.8 V to 2.7 V: HD404052, HD404054, HD404092, HD404094 VCC = 4.0 V to 6.0 V: 5, 6 HD40A4052,HD40A4054 1, 7 2, 7 1, 7 2, 7 1, 7 2, 7 1, 7 2, 7 8 8 9 10 9 10
-- External clock high width t CPH OSC 1 105 49 External clock low width t CPL OSC 1 105 49 External clock rise time t CPr OSC 1 -- -- External clock fall time t CPf OSC 1 -- -- INT0, INT1, EVND high width INT0, INT1, EVND low width RESET low width STOPC low width RESET rise time STOPC rise time t IH t IL t RSTL t STPL t RSTr t STPr INT0, INT1, 2 EVND INT0, INT1, 2 EVND RESET STOPC RESET STOPC 2 1 -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
7.5 -- -- -- -- 20 10 20 10 -- -- -- -- 20 20
ms ns ns ns ns ns ns ns ns t cyc t cyc t cyc t RC ms ms
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Item Input capacitance Symbol Pin(s) Cin Min Typ -- -- -- Max 15 30 15 Unit pF pF pF Test Condition f = 1 MHz, Vin = 0 V f = 1 MHz, Vin = 0 V f = 1 MHz, Vin = 0 V: HD404052, HD404054, HD404092, HD404094, HD40A4052,HD40A4054 f = 1 MHz, Vin = 0 V: HD4074054, HD4074094 VCC = 2.7 V to 5.5 V: 9 HD4074054, HD4074094 VCC = 2.7 V to 6.0 V: HD404052, HD404054, HD404092, HD404094 -- -- -- -- 4 20 t cyc t cyc VCC = 4.0 V to 6.0 V: 11 HD40A4052,HD40A4054 VCC = 1.8 V to 2.7 V: HD404052, HD404054, HD404092, HD404094 Notes All pins except -- D13 D4-D 7 D4-D 7 D13 -- --
-- Analog comparator t CSTB stabilization time COMP0, COMP1 --
-- --
180 2
pF t cyc
Notes: 1. 2. 3. 4. 5.
Applies to HD404052, HD404054, HD4074054, HD404092, HD404094, HD4074094. Applies to HD40A4052, HD40A4054. SEL = 1 SEL = 0 The oscillation stabilization time is the period required for the oscillator to stabilize after V CC reaches 2.7 (HD4074054, HD4074094)/1.8 (HD404052, HD404054, HD404092, HD404094) /4.0 (HD40A4052, HD40A4054)V at power-on, or after RESET input goes low or STOPC input goes low when stop mode is cancelled. At power-on or when stop mode is cancelled, RESET or STOPC must be input for at least tRC to ensure the oscillation stabilization time. If using a ceramic oscillator, contact its manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. 6. Applies to ceramic oscillator only. 7. Refer to figure 68. 8. Refer to figure 69. 9. Refer to figure 70. 10. Refer to figure 71. 11. Analog comparator stabilization time is the period for the analog comparator to stabilize and for correct data to be read after entering RD 0/COMP0, RD1/COMP1 into analog input mode.
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Serial Interface Timing Characteristics (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V to 6.0 V, GND = 0 V, Ta = -20C to +75C; HD40A4052, HD40A4054: V CC = 4.0 V to 6.0 V, GND = 0 V, T a = -20C to +75C; HD4074054, HD4074094: VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified) During Transmit Clock Output
Item Transmit clock cycle time Transmit clock high width Transmit clock low width Transmit clock rise time Symbol t Scyc t SCKH t SCKL t SCKr Pin(s) SCK 1 SCK 1 SCK 1 SCK 1 Min 1 0.5 0.5 -- -- Transmit clock fall time t SCKf SCK 1 -- -- Serial output data delay time t DSO SO1 -- -- Serial input data t SSI setup time SI 1 300 150 Serial input data t HSI hold time SI 1 300 150 Note: Typ -- -- -- 100 -- 100 -- -- -- -- -- -- -- Max -- -- -- -- 80 -- 80 500 200 -- -- -- -- Unit t cyc t Scyc t Scyc ns ns ns ns ns ns ns ns ns ns Load shown in figure 73 Load shown in figure 73 Test Condition Load shown in figure 73 Load shown in figure 73 Load shown in figure 73 Load shown in figure 73 Note 1 1 1 1, 2 1, 3 1, 2 1, 3 1, 2 1, 3 1, 2 1, 3 1, 2 1, 3
1. Refer to figure 72. 2. Applies to HD404052, HD404054, HD404092, HD404094, HD4074054, HD4074094. 3. Applies to HD40A4052, HD40A4054.
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During Transmit Clock Input
Item Transmit clock cycle time Transmit clock high width Transmit clock low width Transmit clock rise time Symbol t Scyc t SCKH t SCKL t SCKr Pin(s) SCK 1 SCK 1 SCK 1 SCK 1 Min 1 0.5 0.5 -- -- Transmit clock fall time t SCKf SCK 1 -- -- Serial output data delay time t DSO SO1 -- -- Serial input data t SSI setup time SI 1 300 150 Serial input data t HSI hold time SI 1 300 150 Note: Typ -- -- -- 100 -- 100 -- -- -- -- -- -- -- Max -- -- -- -- 80 -- 80 500 200 -- -- -- -- Unit t cyc t Scyc t Scyc ns ns ns ns ns ns ns ns ns ns Load shown in figure 73 Test Condition Note 1 1 1 1, 2 1, 3 1, 2 1, 3 1, 2 1, 3 1, 2 1, 3 1, 2 1, 3
1. Refer to figure72. 2. Applies to HD404052, HD404054, HD404092, HD404094, HD4074054, HD4074094. 3. Applies to HD40A4052, HD40A4054.
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OSC 1
1/fCP VCC - 0.3 V 0.3 V tCPH tCPr tCPf tCPL
Figure 68 External Clock Timing
RESET
0.9 VCC 0.1 V CC
tRSTL tRSTr
Figure 69 Interrupt Timing
INT0 , INT1, EVND
0.9 VCC 0.1 VCC
t IH
t IL
Figure 70 Reset Timing
STOPC
0.9 VCC 0.1 V CC
tSTPL tSTPr
Figure 71 STOPC Timing
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t Scyc t SCKf SCK 1 VCC - VH (0.9 VCC )* 0.4 V (0.1 VCC )* t DSO SO 1 VCC - VH 0.4 V t SSI SI 1 0.9 V CC 0.1 V CC t HSI t SCKL t SCKH t SCKr
Note: * VCC - VH and 0.4 V are the threshold voltages for transmit clock output. VH = 1.0 V : HD404052, HD404054, HD4074054, HD404092, HD404094, HD4074094 VH = 2.0 V : HD40A4052, HD40A4054 0.9 VCC and 0.1 VCC are the threshold voltages for transmit clock output.
Figure 72 Serial Interface Timing
VCC RL = 2.6 k Test point C 30 pF R 12 k 1S2074 H or equivalent
Figure 73 Timing Load Circuit
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Notes On ROM Out
Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size as 4-kword versions (HD404054, HD404094 and HD40A4054). A 4-kword data size is required to change ROM data to mask manufacturing data since the program used is for a 4-kword version. This limitation apply to the case of using EPROM and the case of using data base.
ROM 2 kwords version: HD404052, HD404092, HD40A4052 Address $0800 to $0FFF $0000 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern and program (2048 words) $07FF $0800 Not used $0FFF Fill this area with all 1s
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HD40(A)4052/HD40(A)4054 Option List
Please check off the appropriate applications and enter the necessary information.
Date of order Customer Department 1. ROM size HD404052: 2-kword HD404054: 4-kword HD40A4052: 2-kword HD40A4054: 4-kword Name ROM code name LSI number / /
2. ROM code media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS.
3. Oscillator for OSC1 and OSC2 Ceramic oscillator Crystal oscillator External clock f= f= f= MHz MHz MHz
4. Stop mode Used Not used
5. Package DP-42S FP-44A
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HD404092/HD404094 Option List
Please check off the appropriate applications and enter the necessary information.
Date of order Customer Department 1. ROM size HD404092: 2-kword HD404094: 4-kword Name ROM code name LSI number / /
2. ROM code media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS.
3. Oscillator for OSC1 and OSC2 Ceramic oscillator Crystal oscillator External clock f= f= f= MHz MHz MHz
4. Stop mode Used Not used
5. Package DP-42S FP-44A
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Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to:
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX
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Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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